1. Field of the Invention
The present invention relates to memory devices based on phase change based memory materials, and to methods for operating such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
In phase change memory, data is stored by causing transitions in an active region of the phase change material between amorphous and crystalline states. FIG. 1 is a distribution of the resistance of a number of memory cells comprising a phase change memory element. The memory cells are programmable to a plurality of resistance states including a high resistance reset (erased) state 102 and at least one lower resistance programmed (set) state 100. Each resistance state has a non-overlapping resistance range.
The difference between the highest resistance R1 of the lower resistance state 100 and the lowest resistance R2 of the high resistance reset state 102 defines a read margin 101 used to distinguish cells in the lower resistance state 100 from those in the high resistance state 102. The data stored in a memory cell can be determined by determining whether the memory cell has a resistance corresponding to the lower resistance state 100 or to the high resistance state 102, for example by measuring whether the resistance of the memory cell is above or below a threshold resistance value RSA 103 within the read margin 101.
The change from the high resistance state 102 to the lower resistance state 100, referred to as a set (or program) operation herein, is generally a lower current operation in which current heats the phase change material above a transition temperature to cause transition from the amorphous to the crystalline state. The change from the lower resistance state 100 to the higher resistance state 102, referred to as a reset operation herein, is generally a higher current operation, which includes a short high density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state.
In order to reliably distinguish between the high resistance state 102 and the lower resistance state 100, and thus properly determine the data value stored in a memory cell, it is important to maintain a relatively large read margin 101. However, due to variations in materials, manufacturing processes, and the operating environment, the reset current needed to change to the higher resistance state 102 will vary among memory cells in an array. This variation in the reset current is illustrated in the example distribution curve 200 of FIG. 2 which is a distribution in the reset current needed among a number of memory cells.
Previous attempts at addressing this variation in the reset current among memory cells in an array include choosing a single, suitably high reset current IRESET 210 of FIG. 2 capable of resetting each of the memory cells in an array to the higher resistance state 102.
However, using the reset current IRESET 210 for each memory cell in an array results in the memory elements of at least some of the memory cells receiving significantly higher current levels than are necessary to cause a transition to the higher resistance state 102 and is referred to as being “over-reset”. Since the phase change material undergoes a phase change as a result of heating, using unnecessarily high current levels can result in electrical and mechanical reliability problems for the memory cell. These problems include the formation of voids at the phase change material/electrode interface due to mechanical stress caused by thermal expansion and material density changes during operation.
Additionally, using significantly higher current levels than necessary can result in problems such as localized heating sufficient to induce diffusion/reaction of electrode and phase change material, and/or cause compositional changes in the phase change material within the active region, resulting in resistive switching performance degradation and possible failure of the memory cell.
It is therefore desirable to provide phase changed based memory devices and methods for operating such devices which provide the current needed to induce a phase change to the high resistance reset state while also avoiding the use of significantly higher levels of current through the phase change material than necessary.